The invention relates generally to transistors, and, more particularly, to heterojunction bipolar transistors.
Heterojunction bipolar transistors (HBTs) have become state of the art, particularly in npn form, for applications in which high switching speeds and high frequency operation are desired. Some applications, such as multiplexer (MUX) or demultiplexer (DMUX) circuits for high-speed optical communications, require HBTs with higher switching speed than currently available. Higher switching speed is attained through a combination of operating at higher current density, shrinking the lateral dimensions of the device, and optimizing the epitaxial layers that comprise the HBT.
Popular material systems from which HBTs are constructed include indium phosphide (InP) and indium aluminum arsenide (InAlAs). InP HBTs are constructed using epitaxially grown layers of different semiconductor materials that are lattice-matched, or nearly lattice-matched, to InP.
In particular, a wide bandgap material such as InP or InAlAs is chosen for the emitter layer, and a narrow bandgap material such indium gallium arsenide (InGaAs) is chosen for the base layer.
Unfortunately, when a wide bandgap material and a narrow bandgap material form an abrupt heterojunction, a large conduction band offset is formed at the emitter-base junction. This conduction band offset results in a large energy spike in the conduction band at the emitter side of the junction. This energy spike increases the emitter-base turn-on voltage, limits the maximum current that can be driven through the device, and increases the emitter-base ideality factor. Increased emitter-base turn-on voltage undesirably increases the power dissipation in the HBT. It also decreases the number of transistors that can be stacked in series. An increased ideality factor and reduced current driveability reduce the speed at which logic circuits, or analog circuits such as amplifiers, can operate.
As mentioned above, HBTs can be fabricated using either InP or InAlAs in the emitter layer. To achieve a low turn-on voltage in HBTs having an InAlAs emitter and an InGaAs base, a standard practice is to use a grading layer between the InAlAs body of the emitter and the InGaAs base.
The grading layer provides a smooth energy transition in the conduction band between the InGaAs base and the InAlAs emitter. Most of the grading layer is formed on the emitter-side of the junction and has the effect of reducing or preventing the formation of the energy spike. The thickness of this grading layer is typically in the range of 14 to 40 nanometers (nm). The grading layer can be formed in a variety of ways. For example, in an HBT having an InAlAs emitter and an InGaAs base, an alloy grading layer (comprising a quaternary layer of InAlGaAs) can be inserted between the base and the emitter body. The composition of such a grading layer varies from predominately InAlAs on the emitter side to predominately InGaAs on the base side.
Alternatively, a chirped superlattice, which comprises a series of pairs of thin layers of InGaAs and InAlAs, in which the fraction of the thickness of the InGaAs to the total thickness of the InGaAs and the InAlAs layer in each pair is varied from xcx9c0 on the emitter end to xcx9c1 on the base end, can be used as a grading layer. Further still, instead of a grading layer, a constant-composition layer of InP has also been used between the emitter and base. The latter solution, while providing an emitter base junction that exhibits better electrical characteristics than an abrupt InAlAs/InGaAs emitter-base junction, still fails to provide a good conduction band match to the base material, and still allows an energy spike to form in the conduction band.
An HBT having an InP emitter and an InGaAs base generally exhibits a smaller energy spike at the emitter-base junction than does an HBT having an InAlAs emitter and an InGaAs base. However, using InP in the emitter layer still results in the formation of an abrupt emitter-base junction that has an energy spike. Therefore, structures to reduce the energy spike have also been implemented in a device having an InP emitter. For example, a thin undoped InGaAs setback layer in the base, or a step alloy grading structure comprising two discrete 7 nm InGaAsP layers, or continuous InGaAsP alloy grading (from InP to InGaAs), or a chirped superlattice comprising InGaAs and InP layer pairs are each solutions that have been used to minimize the conduction band energy spike at the emitter-base junction. Unfortunately, using layers of material in which one material includes arsenic and the other material includes phosphorous leads to a large number of arsenide-phosphide interfaces. An arsenide-phosphide interface is difficult to produce and typically result in strained growth, which may lead to dislocations in the epitaxial layers that form the grading structure.
In addition to band energy considerations, the choice of emitter material and structure can affect the passivation of the extrinsic base surface of the HBT, and hence can affect the current gain. One way of effectively passivating the extrinsic base surface is to leave a thin depleted layer of emitter material (typically known as a ledge) in the extrinsic base region. The ledge passivates the surface of the base layer by reducing the recombination of minority carriers injected into the base, which, while negligible at the base-ledge surface, can be very large at an exposed base layer surface.
It is also desirable to minimize the base-collector capacitance and base resistance in an HBT. Many modern HBTs use a self-aligned base contact to minimize the extrinsic base-collector capacitance and base resistance. One common approach to implementing this fabrication technique is to undercut the emitter mesa so that when metallization for the base contact is deposited after emitter mesa formation, a gap between the emitter and the base contact is maintained. In order to form the undercut, the emitter and base should be fabricated so that an etchant can be introduced that removes the emitter material, but not the base (or ledge, if present).
Therefore, there is a need for an HBT having an InP emitter and an InGaAs base, and that exhibits superior emitter-base junction behavior at high current density. Straightforward growth of the epitaxial layers and good etch selectivity between the emitter and surrounding materials are also desired.
The invention is a heterojunction bipolar transistor (HBT), including an emitter formed from a first semiconductor material, a base formed from a second semiconductor material, and a grading structure between the emitter and the base. The grading structure comprises a semiconductor material containing at least one element not present in the first and second semiconductor materials, where the grading structure has a conduction band energy substantially equal to a conduction band energy of the base at an interface between the base and the grading structure, and where the grading structure has a conduction band energy substantially equal to a conduction band energy of the emitter at an interface between the emitter and the grading structure. The grading structure provides a gradual change in conduction band energy at the emitter-base junction and facilitates selective etching of the grading structure with respect to the emitter.